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DG201A, DG202
Data Sheet June 1999 File Number
3117.2
Quad SPST, CMOS Analog Switches
The DG201A and DG202 quad SPST analog switches are designed using Intersil's 44V CMOS process. These bidirectional switches are latch-proof and feature breakbefore-make switching. Designed to block signals up to 30VP-P in the OFF state, the DG201A and DG202 offer the advantages of low ON resistance (175), wide input signal range (15V) and provide both TTL and CMOS compatibility. The DG201A and DG202 are specification and pinout compatible with the industry standard devices.
Features
* Input Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . . 15V * Low rDS(ON) (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . 175 * TTL, CMOS Compatible * Latch-Up Proof * True Second Source * Maximum Supply Ratings. . . . . . . . . . . . . . . . . . . . . . 44V * Logic Inputs Accept Negative Voltages
Ordering Information
PART NUMBER DG201AAK DG201ABK DG201ACJ DG201ACY DG202AK DG202CJ TEMP. RANGE (oC) -55 to 125 -25 to 85 0 to 70 0 to 70 -55 to 125 0 to 70 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld CERDIP 16 Ld PDIP PKG. NO. F16.3 F16.3 E16.3 M16.3 F16.3 E16.3
Functional Block Diagrams
DG201A
S1 IN1 D1 S2 IN2 D2 S3 IN3 D3 S4
Pinout
DG201A, DG202 (CERDIP, PDIP, SOIC) TOP VIEW
1 2 3 4 5 6 7 8 16 IN2 15 D2 14 S2 13 V+ (SUBSTRATE) 12 NC 11 S3 10 D3 9 IN3
IN4 D4
DG202
S1 IN1 D1 S2 IN2 D2 S3 IN3 D3 S4 IN4 D4
IN1 D1 S1 VGND S4 D4 IN4
SWITCHES SHOWN FOR LOGIC "1" INPUT
TRUTH TABLE LOGIC 0 1 DG201A ON OFF DG202 OFF ON
Logic "0" 0.8V, Logic "1" 2.4V
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
DG201A, DG202
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V VIN to Ground (Note 1) . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V VS or VD to V+ (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . +2 to (V-) -2V VS or VD to V- (Note 1) . . . . . . . . . . . . . . . . . . . . . . . -2 to (V+) +2V Current, any Terminal Except S or D . . . . . . . . . . . . . . . . . . . . 30mA Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 70mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 20 PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range "A" Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC "B" Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC "C" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Signals on VS , VD , or VIN exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V+ = 15V, V- = -15V, GND = 0V, TA = 25oC "A" SUFFIX "B" AND "C" SUFFIX MAX MIN (NOTE 3) TYP MAX UNITS
PARAMETER DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Charge Injection, Q OFF Isolation, OIRR Crosstalk (Channel to Channel), CCRR Source OFF Capacitance, CS(OFF) Drain OFF Capacitance, CD(OFF) Channel ON Capacitance, CD(ON) + CS(ON) DIGITAL INPUT CHARACTERISTICS Input Current with Voltage High, IIH
TEST CONDITIONS
MIN
(NOTE 3) TYP
See Figure 1 See Figure 1 CL = 1nF, RS = 0, VS = 0V VIN = 5V, RL = 75, VS = 2.0V, f = 100kHz f = 140kHz, VIN = 5V, VS = VD = 0V
-
480 370 20 70 -90 5.0 5.0 16
600 450 -
-
480 370 20 70 -90 5.0 5.0 16
-
ns ns pC dB dB pF pF pF
VIN = 2.4V VIN = 15V
-1.0 -1.0
-0.0004 0.003 -0.0004
1.0 -
-1.0 -1.0
-0.0004 0.003 -0.0004
1.0 -
A A A
Input Current with Voltage Low, IIL ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) Source OFF Leakage Current, IS(OFF)
VIN = 0V
-15 VD = 10V, VIN = 0.8V (DG201A) IS = 1mA, VIN = 2.4V (DG202) VIN = 2.4V (DG201A) VIN = 0.8V (DG202) VS = 14V, VD = -14V VS = -14V, VD = 14V VS = -14V, VD = 14V VS = 14V, VD = -14V -1.0 -1.0
115 0.01 -0.02 0.01 -0.02
15 175 1.0 1.0 -
-15 -5.0 -5.0
115 0.01 -0.02 0.01 -0.02
15 200 5.0 5.0 -
V nA nA nA nA
Drain OFF Leakage Current, ID(OFF)
4-2
DG201A, DG202
Electrical Specifications
V+ = 15V, V- = -15V, GND = 0V, TA = 25oC (Continued) "A" SUFFIX PARAMETER Drain ON Leakage Current, ID(ON) (Note 5) TEST CONDITIONS VIN = 0.8V (DG201A) VIN = 2.4V (DG202) VD = VS = 14V VD = VS = -14V MIN -1.0 (NOTE 3) TYP 0.1 -0.15 MAX 1.0 "B" AND "C" SUFFIX MIN -5.0 (NOTE 3) TYP 0.1 -0.15 MAX 5.0 UNITS A A
POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ Negative Supply Current, IAll Channels ON or OFF -1 0.9 -0.3 2 -1 0.9 -0.3 2 mA mA
Electrical Specifications
V+ = 15V, V- = -15V, GND = 0V, TA Over Operating Temperature Range "A" SUFFIX (NOTE 3) TYP
PARAMETER DIGITAL INPUT CHARACTERISTICS Input Current with Voltage High, IIH VIN = 2.4V VIN = 15V Input Current with Voltage Low, IIL ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) Source OFF Leakage Current, IS(OFF) VIN = 0V
TEST CONDITIONS
MIN
MAX
UNITS
-10 -10
-
10 -
A A A
-15 VD = 10V, VIN = 0.8V (DG201A) IS = 1mA, VIN = 2.4V (DG202) VIN = 2.4V (DG201A) VIN = 0.8V (DG202) VS = 14V, VD = -14V VS = -14V, VD = 14V VS = -14V, VD = 14V VS = 14V, VD = -14V -
-
15 250
V nA nA nA nA A A
-100 -100 -200
-
100 100 200 -
Drain OFF Leakage Current, ID(OFF)
Drain ON Leakage Current, ID(ON) (Note 5)
VIN = 0.8V (DG201A) VIN = 2.4V (DG202)
VD = VS = 14V VD = VS = -14V
NOTES: 3. Typical values are for design aid only, not guaranteed and not subject to production testing. 4. The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data sheet. 5. ID(ON) is leakage from driver into ON switch.
4-3
DG201A, DG202 Test Circuits and Waveforms
LOGIC "0" = SWITCH ON 50% VO = VS RL RL + rDS(ON) 15V V+ SWITCH INPUT VS = 2V VS 90% SWITCH OUTPUT 90% LOGIC INPUT IN1 RL 1k S1 D1 SWITCH OUTPUT VO CL 35pF
LOGIC 3V INPUT tr < 20ns tf < 20ns SWITCH INPUT
tON
tOFF
GND V-15V
(REPEAT TEST FOR IN2 , IN3 AND IN4)
Logic shown for DG201A, invert for DG202.
FIGURE 1. tON AND tOFF SWITCHING TEST CIRCUIT AND MEASUREMENT POINTS
VO RS SX DX VO SWITCH OUTPUT
VS
INX
CL = 1nF INX ON OFF ON
NOTES: 6. VO = Measured voltage error due to charge injection. 7. The error in coulombs is Q = CL x VO . FIGURE 2. CHARGE INJECTION TEST CIRCUIT AND MEASUREMENT POINTS
+15V C C
+15V
SIGNAL GENERATOR VS
V+ VS
SIGNAL GENERATOR VS INX VIN ANALYZER CHAN A 0V, 2.4V
3
V+ VS1
VD1
50
IN1
IN2
0V, 2.4V
ANALYZER CHAN A CHAN B RL -15V VD GND VC
CHAN B RL
VD2 GND
VS2 VC -15V
NC
C = 0.001F||0.1F Chip Capacitors
VS OIRR = 20 Log ------VD
C = 0.001F||0.1F Chip Capacitors
V S1 CCRR = 20 Log ----------V D2
FIGURE 3. OFF ISOLATION TEST CIRCUIT
FIGURE 4. CHANNEL TO CHANNEL CROSSTALK TEST CIRCUIT
4-4
DG201A, DG202 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150
2.54 BSC 7.62 BSC 2.93 16 10.92 3.81
4-5
DG201A, DG202 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
4-6
DG201A, DG202 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M16.3 (JEDEC MS-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 10.10 7.40 MAX 2.65 0.30 0.51 0.32 10.50 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.3977 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.4133 0.2992
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.394 0.010 0.016 16 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 16 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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